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Integrated Circuit Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
FEATURES
* 5 differential 3.3V LVPECL outputs * Selectable differential clock inputs * CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Output frequency range: 31.25MHz to 700MHz * Input frequency range: 31.25MHz to 700MHz * VCO range: 250MHz to 700MHz * Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 * External feedback for "zero delay" clock regeneration with configurable frequencies * Cycle-to-cycle jitter: 25ps (maximum) * Output skew: 25ps (maximum) * Static phase offset: 50ps 100ps * 3.3V supply voltage * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8735-01 is a highly versatile 1:5 Differential-to-3.3V LVPECL clock generator and a HiPerClockSTM member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8735-01 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-toinput frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
ICS
BLOCK DIAGRAM
PLL_SEL
/1, /2, /4, /8, /16, /32, /64
PIN ASSIGNMENT
Q0 nQ0
VCC PLL_SEL SEL3 VCCO VCCA nQ4 VEE Q4
0
Q1 nQ1 Q2 nQ2
CLK0 nCLK0 CLK1 nCLK1 CLK_SEL FB_IN nFB_IN
32 31 30 29 28 27 26 25 SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VCC nFB_IN FB_IN SEL2 VEE nQ0 Q0 VCCO
0
1
1
Q3 nQ3
24 23 22
VCCO Q3 nQ3 Q2 nQ2 Q1 nQ1 VCCO
PLL
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Q4 nQ4
ICS8735-01
21 20 19 18 17
SEL0 SEL1 SEL2 SEL3 MR
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 32-Lead VFQFN 5mm x 5mm x 0.95 package body K Package Top View
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Integrated Circuit Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 Name SEL0 SEL1 CLK0 nCLK0 CLK 1 nCLK1 CLK_SEL Input Input Input Input Input Input Input Type Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects CLK1, nCLK1. Pulldown When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go high. Pulldown When logic LOW, the internal dividers and the otuputs are enabled. LVCMOS / LVTTL interface levels. Core supply pins. Pullup Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Negative supply pins. Differential output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Analog supply pin. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock.When HIGH, selects PLL. LVCMOS / LVTTL interface levels.
8 9 , 32 10 11 12 13, 28 14, 15 16, 17, 24, 25 18, 19 20, 21 22, 23 26, 27 29 30 31
MR VCC nFB_IN FB_IN SEL2 VEE nQ0, Q0 VCCO nQ1, Q1 nQ2, Q2 nQ3, Q3 nQ4, Q4 SEL3 VCCA PLL_SEL
Input Power Input Input Input Power Output Power Output Output Output Output Input Power Input
Pullup
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
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ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q4, nQ0:nQ4 /1 /1 /1 /1 /2 /2 /2 /4 /4 /8 x2 x2 x2 x4 x4 x8
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S E L1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference Frequency Range (MHz)* 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 250 - 700 125 - 350 62.5 - 175 250 - 700 125 - 350 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 62.5 - 175 31.25 - 87.5 31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is 250 to 700MHz.
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
8735AY-01
SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
S E L1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Outputs PLL_SEL = 0 PLL Bypass Mode Q0:Q4, nQ0:nQ4 /4 /4 /4 /8 /8 /8 / 16 / 16 / 32 / 64 /2 /2 /4 /1 /2 /1
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Integrated Circuit Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5 V -0.5V to VCCO + 0.5V 47.9C/W (0 lfpm) 34.8C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, VO Package Thermal Impedance, JA 32 Lead LQFP 32 Lead VFQFN Storage Temperature, TSTG
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter VCC VCCA VCCO IEE ICCA Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 150 15 Units V V V mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter VIH VIL IIH Input High Voltage Input Low Voltage Input High Current CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 PLL_SEL VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A
IIL
Input Low Current
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter IIH IIL VPP Input High Current Input Low Current CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN Test Conditions VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -150 0.15 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCMR NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0. 6 Typical Maximum VCCO - 1.0 VCCO - 1.7 1.0 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol fIN Parameter Input Frequency CLK0, nCLK0, CLK1, nCLK1 Test Conditions PLL_SEL = 1 PLL_SEL = 0 Minimum 31.25 Typical Maximum 700 700 Units MHz MHz
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tPD t(O) t sk(o) t jit(cc) t jit() tL tR tF Parameter Output Frequency Propagation Delay; NOTE 1 Static Phase Offset; NOTE 2, 5 Output Skew; NOTE 3, 5 Cycle-to-Cycle Jitter; NOTE 5, 6 Phase Jitter; NOTE 4, 5, 6 PLL Lock Time Output Rise Time Output Fall Time 20% to 80% @ 50MHz 20% to 80% @ 50MHz 300 300 PLL_SEL = 0V, f 700MHz PLL_SEL = 3.3V 3.4 -50 50 Test Conditions Minimum Typical Maximum 700 4.2 150 25 25 50 1 700 700 Units MHz ns ps ps ps ps ms ps ps %
odc Output Duty Cycle 47 53 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz.
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ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V V CC
VCC, VCCA, VCCO
Qx
SCOPE
LVPECL
VEE
nQx
nCLK0, nCLK1 V CLK0, CLK1 VEE
PP
Cross Points
V
CMR
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
nQ0:nQ4 Q0:Q4
tcycle
n
tsk(o)
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
OUTPUT SKEW
80% Clock Outputs 80% VSW I N G 20% tR tF 20%
CYCLE-TO-CYCLE JITTER
nQ0:nQ4 Q0:Q4
Pulse Width t
PERIOD
odc =
t PW t PERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nCLK0, nCLK1 CLK0, CLK1
nFB_IN FB_IN
nCLK0, nCLK1 CLK0, CLK1 nQ0:nQ4 Q0:Q4
tPD
t(O)
tjit(O) = t(O) -- t(O) mean = Phase Jitter t(O) mean = Static Phase Offset
(where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges)
PROPAGATION DELAY
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PHASE JITTER & STATIC PHASE OFFSET
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tcycle n+1
VOH VOL VOH VOL
Integrated Circuit Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 1A and 1B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125 125
FOUT
FIN
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 1A. LVPECL OUTPUT TERMINATION
FIGURE 1B. LVPECL OUTPUT TERMINATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
Zo = 50 Ohm
LVDS_Driv er
CLK
R1 100
nCLK
Receiv er
Zo = 50 Ohm
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
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ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
3.3V VCC .01F 10
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8735-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 4 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
V CCA .01F 10F
FIGURE 4. POWER SUPPLY FILTERING
LAYOUT GUIDELINE
The schematic of the ICS8735-01 layout example is shown in Figure 5A. The ICS8735-01 recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The layout in the actual system will
VCC
depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board.
SP = Space (i.e. not intstalled)
R7 RU2 SP RU3 1K RU4 1K RU5 SP RU6 1K RU7 SP CLK_SEL PLL_SEL SEL0 SEL1 SEL2 SEL3 PLL_SEL SEL3 VCCA VCC
SEL[3:0] = 0101, Divide by 2
10 C11 0.01u C16 10u Zo = 50 Ohm +
(77.76 MHz)
RD2 1K
RD3 SP
RD4 SP
RD5 1K
RD6 SP
RD7 1K
VCC
VCCO Zo = 50 Ohm
LVPECL_input
U1 3.3V
R5 50
R4 50
(155.52 MHz)
Zo = 50 Ohm SEL0 SEL1 1 2 3 4 5 6 7 8
VCC PLL_SEL VCCA SEL3 VEE Q4 nQ4 VCCO
32 31 30 29 28 27 26 25
Zo = 50 Ohm CLK_SEL 3.3V PECL Driver R8 50 R9 50
VCC nFB_IN FB_IN SEL2 VEE nQ0 Q0 VCCO
SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR
VCCO Q3 nQ3 Q2 nQ2 Q1 nQ1 VCCO
24 23 22 21 20 19 18 17
R6 50
Output Termination Example
Bypass capacitor located near the power pins
(U1-9)
VCC
(U1-32)
9 10 11 12 13 14 15 16
8735-01
VCC=3.3V
C1 0.1uF C6 0.1uF
VCCO=3.3V
R10 50
SEL2
(U1-16)
R2 50 R1 50 C2 0.1uF R3 50
VCCO
(U1-17)
(U1-24)
(U1-25)
C4 0.1uF
C5 0.1uF
C7 0.1uF
FIGURE 5A. ICS8735-01 LVPECL ZERO DELAY BUFFER SCHEMATIC EXAMPLE
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The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. * The differential 50 output traces should have same length. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. * Make sure no other signal traces are routed between the clock trace pair. * The matching termination resistors should be located as close to the receiver input pins as possible.
POWER
AND
GROUNDING
Place the decoupling capacitors C1, C6, C2, C4, C5, and C7, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape
GND
R7 C16 C11 C7 C6 C5
VCCO
U1
Pin 1
VCC
VCCA
VIA
50 Ohm Traces
C4 C1 C2
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8735-01
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ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8735-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8735-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 520mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power_MAX (3.465V, with all outputs switching) = 520mW + 151mW = 671mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 7A below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.671W * 42.1C/W = 98C. This is well below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7A. THERMAL RESISTANCE JA
FOR
32-PIN LQFP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B. JAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE
JA 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
8735AY-01
34.8C/W
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. F NOVEMBER 12, 2004
Integrated Circuit Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 8A. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP PACKAGE
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 8B. JAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE
JA 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 34.8C/W
TRANSISTOR COUNT
The transistor count for ICS8735-01 is: 2969
8735AY-01
www.icst.com/products/hiperclocks.html
13
REV. F NOVEMBER 12, 2004
Integrated Circuit Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 9A. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L 0.45 0 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
--ccc Reference Document: JEDEC Publication 95, MS-026
8735AY-01
www.icst.com/products/hiperclocks.html
14
REV. F NOVEMBER 12, 2004
Integrated Circuit Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
32 LEAD VFQFN
PACKAGE OUTLINE - K SUFFIX
FOR
TABLE 9B. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 1.25 0.30 1.25 5.0 3.25 0.50 0.18 0.50 BASIC 8 8 5.0 3.25 0.80 0 0.25 Reference 0.30 MINIMUM 32 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
8735AY-01
www.icst.com/products/hiperclocks.html
15
REV. F NOVEMBER 12, 2004
Integrated Circuit Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Marking ICS8735AY-01 ICS8735AY-01 ICS8735AK-01 ICS8735AK-01 Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel 32 Lead VFQFN 32 Lead VFQFN on Tape and Reel Count 250 per tray 1000 490 per Tray 2500 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS8735AY-01 ICS8735AY-01T ICS8735AK-01 ICS8735AK-01T
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8735AY-01
www.icst.com/products/hiperclocks.html
16
REV. F NOVEMBER 12, 2004
Integrated Circuit Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
REVISION HISTORY SHEET Description of Change tPD row changed the Test Condtions from 0MHz < f 700MHz to f 700MHz. Date
Rev
Table
Page
B
T5
5
C C C C C
T4A T3A T6 Figure 11 T2
4 1 3 5 10 10 2 6 8 5 5 2 4
t(O) row changed Parameter name from PLL Reference Zero Delay to Static Phase Offset. tjit() row changed 85 Max. to 50 Max. Added ICCA row.
Updated Block Diagram. Added note at end of the table. Added Note 6. Revised Figure 11, LVPECL Zero Delay Buffer Schematic Example Added Termination for LVPECL Outputs section Pin Description Table - revised MR description. 3.3V Output Load Test Circuit Diagram, revised VEE equation from "-1.3V 0.135V" to " -1.3V 0.165V". Revised Output Rise/Fall Time Diagram. LVPECL table - corrected VSWING from 0.9 max. to 1.0 max. AC Table - changed tPD from 3.6 min. to 3.4 min, deleted 3.9 typical. Updated VCC pin description to read Core supply pins from Positive supply pins. Updated VCC to read Core Supply Voltage from Positive Supply Voltage. IEE, deleted 100mA typical and added 150mA Maximum. Updated format. Pin Description Table - updated MR description. Corrected LVPECL Zero Delay Buffer Schematic Example. Add 32 Lead VFQFN package throughout data sheet. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. Added Differential Clock Input Interface Application Section.
10/12/01
10/30/01 11/1/01 11/19/01 12/3/01 6/3/02
C T4D D T6 T1 E T4A
8/19/02
9/17/02
12/3/02
E
T1
2 8
1/31/03
F
T2
2 8
11/12/04
8735AY-01
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17
REV. F NOVEMBER 12, 2004

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